// Peripheral: RCC_Periph  Reset and Clock Control.
// Instances:
//  RCC  mmap.RCC_BASE
// Registers:
//  0x00 32  CR         Clock control register.
//  0x04 32  PLLCFGR    PLL configuration register.
//  0x08 32  CFGR       Clock configuration register.
//  0x0C 32  CIR        Clock interrupt register.
//  0x10 32  AHB1RSTR   AHB1 peripheral reset register.
//  0x14 32  AHB2RSTR   AHB2 peripheral reset register.
//  0x18 32  AHB3RSTR   AHB3 peripheral reset register.
//  0x20 32  APB1RSTR   APB1 peripheral reset register.
//  0x24 32  APB2RSTR   APB2 peripheral reset register.
//  0x30 32  AHB1ENR    AHB1 peripheral clock register.
//  0x34 32  AHB2ENR    AHB2 peripheral clock register.
//  0x38 32  AHB3ENR    AHB3 peripheral clock register.
//  0x40 32  APB1ENR    APB1 peripheral clock enable register.
//  0x44 32  APB2ENR    APB2 peripheral clock enable register.
//  0x50 32  AHB1LPENR  AHB1 peripheral clock enable in low power mode register.
//  0x54 32  AHB2LPENR  AHB2 peripheral clock enable in low power mode register.
//  0x58 32  AHB3LPENR  AHB3 peripheral clock enable in low power mode register.
//  0x60 32  APB1LPENR  APB1 peripheral clock enable in low power mode register.
//  0x64 32  APB2LPENR  APB2 peripheral clock enable in low power mode register.
//  0x70 32  BDCR       Backup domain control register.
//  0x74 32  CSR        Clock control & status register.
//  0x80 32  SSCGR      Spread spectrum clock generation register.
//  0x84 32  PLLI2SCFGR PLLI2S configuration register.
//  0x8C 32  DCKCFGR    Dedicated Clocks configuration register.
// Import:
//  stm32/o/f411xe/mmap
package rcc

// DO NOT EDIT THIS FILE. GENERATED BY stm32xgen.

const (
	HSION     CR = 0x01 << 0  //+
	HSIRDY    CR = 0x01 << 1  //+
	HSITRIM   CR = 0x1F << 3  //+
	HSICAL    CR = 0xFF << 8  //+
	HSEON     CR = 0x01 << 16 //+
	HSERDY    CR = 0x01 << 17 //+
	HSEBYP    CR = 0x01 << 18 //+
	CSSON     CR = 0x01 << 19 //+
	PLLON     CR = 0x01 << 24 //+
	PLLRDY    CR = 0x01 << 25 //+
	PLLI2SON  CR = 0x01 << 26 //+
	PLLI2SRDY CR = 0x01 << 27 //+
)

const (
	HSIONn     = 0
	HSIRDYn    = 1
	HSITRIMn   = 3
	HSICALn    = 8
	HSEONn     = 16
	HSERDYn    = 17
	HSEBYPn    = 18
	CSSONn     = 19
	PLLONn     = 24
	PLLRDYn    = 25
	PLLI2SONn  = 26
	PLLI2SRDYn = 27
)

const (
	PLLM       PLLCFGR = 0x3F << 0  //+
	PLLN       PLLCFGR = 0x1FF << 6 //+
	PLLP       PLLCFGR = 0x03 << 16 //+
	PLLSRC     PLLCFGR = 0x01 << 22 //+
	PLLSRC_HSE PLLCFGR = 0x01 << 22
	PLLSRC_HSI PLLCFGR = 0x00 << 22
	PLLQ       PLLCFGR = 0x0F << 24 //+
)

const (
	PLLMn   = 0
	PLLNn   = 6
	PLLPn   = 16
	PLLSRCn = 22
	PLLQn   = 24
)

const (
	SW          CFGR = 0x03 << 0  //+ SW[1:0] bits (System clock Switch).
	SW_HSI      CFGR = 0x00 << 0  //  HSI selected as system clock.
	SW_HSE      CFGR = 0x01 << 0  //  HSE selected as system clock.
	SW_PLL      CFGR = 0x02 << 0  //  PLL selected as system clock.
	SWS         CFGR = 0x03 << 2  //+ SWS[1:0] bits (System Clock Switch Status).
	SWS_HSI     CFGR = 0x00 << 2  //  HSI oscillator used as system clock.
	SWS_HSE     CFGR = 0x01 << 2  //  HSE oscillator used as system clock.
	SWS_PLL     CFGR = 0x02 << 2  //  PLL used as system clock.
	HPRE        CFGR = 0x0F << 4  //+ HPRE[3:0] bits (AHB prescaler).
	HPRE_DIV1   CFGR = 0x00 << 4  //  SYSCLK not divided.
	HPRE_DIV2   CFGR = 0x08 << 4  //  SYSCLK divided by 2.
	HPRE_DIV4   CFGR = 0x09 << 4  //  SYSCLK divided by 4.
	HPRE_DIV8   CFGR = 0x0A << 4  //  SYSCLK divided by 8.
	HPRE_DIV16  CFGR = 0x0B << 4  //  SYSCLK divided by 16.
	HPRE_DIV64  CFGR = 0x0C << 4  //  SYSCLK divided by 64.
	HPRE_DIV128 CFGR = 0x0D << 4  //  SYSCLK divided by 128.
	HPRE_DIV256 CFGR = 0x0E << 4  //  SYSCLK divided by 256.
	HPRE_DIV512 CFGR = 0x0F << 4  //  SYSCLK divided by 512.
	PPRE1       CFGR = 0x07 << 10 //+ PRE1[2:0] bits (APB1 prescaler).
	PPRE1_DIV1  CFGR = 0x00 << 10 //  HCLK not divided.
	PPRE1_DIV2  CFGR = 0x04 << 10 //  HCLK divided by 2.
	PPRE1_DIV4  CFGR = 0x05 << 10 //  HCLK divided by 4.
	PPRE1_DIV8  CFGR = 0x06 << 10 //  HCLK divided by 8.
	PPRE1_DIV16 CFGR = 0x07 << 10 //  HCLK divided by 16.
	PPRE2       CFGR = 0x07 << 13 //+ PRE2[2:0] bits (APB2 prescaler).
	PPRE2_DIV1  CFGR = 0x00 << 13 //  HCLK not divided.
	PPRE2_DIV2  CFGR = 0x04 << 13 //  HCLK divided by 2.
	PPRE2_DIV4  CFGR = 0x05 << 13 //  HCLK divided by 4.
	PPRE2_DIV8  CFGR = 0x06 << 13 //  HCLK divided by 8.
	PPRE2_DIV16 CFGR = 0x07 << 13 //  HCLK divided by 16.
	RTCPRE      CFGR = 0x1F << 16 //+
	MCO1        CFGR = 0x03 << 21 //+
	I2SSRC      CFGR = 0x01 << 23 //+
	MCO1PRE     CFGR = 0x07 << 24 //+
	MCO2PRE     CFGR = 0x07 << 27 //+
	MCO2        CFGR = 0x03 << 30 //+
)

const (
	SWn      = 0
	SWSn     = 2
	HPREn    = 4
	PPRE1n   = 10
	PPRE2n   = 13
	RTCPREn  = 16
	MCO1n    = 21
	I2SSRCn  = 23
	MCO1PREn = 24
	MCO2PREn = 27
	MCO2n    = 30
)

const (
	LSIRDYF     CIR = 0x01 << 0  //+
	LSERDYF     CIR = 0x01 << 1  //+
	HSIRDYF     CIR = 0x01 << 2  //+
	HSERDYF     CIR = 0x01 << 3  //+
	PLLRDYF     CIR = 0x01 << 4  //+
	PLLI2SRDYF  CIR = 0x01 << 5  //+
	CSSF        CIR = 0x01 << 7  //+
	LSIRDYIE    CIR = 0x01 << 8  //+
	LSERDYIE    CIR = 0x01 << 9  //+
	HSIRDYIE    CIR = 0x01 << 10 //+
	HSERDYIE    CIR = 0x01 << 11 //+
	PLLRDYIE    CIR = 0x01 << 12 //+
	PLLI2SRDYIE CIR = 0x01 << 13 //+
	LSIRDYC     CIR = 0x01 << 16 //+
	LSERDYC     CIR = 0x01 << 17 //+
	HSIRDYC     CIR = 0x01 << 18 //+
	HSERDYC     CIR = 0x01 << 19 //+
	PLLRDYC     CIR = 0x01 << 20 //+
	PLLI2SRDYC  CIR = 0x01 << 21 //+
	CSSC        CIR = 0x01 << 23 //+
)

const (
	LSIRDYFn     = 0
	LSERDYFn     = 1
	HSIRDYFn     = 2
	HSERDYFn     = 3
	PLLRDYFn     = 4
	PLLI2SRDYFn  = 5
	CSSFn        = 7
	LSIRDYIEn    = 8
	LSERDYIEn    = 9
	HSIRDYIEn    = 10
	HSERDYIEn    = 11
	PLLRDYIEn    = 12
	PLLI2SRDYIEn = 13
	LSIRDYCn     = 16
	LSERDYCn     = 17
	HSIRDYCn     = 18
	HSERDYCn     = 19
	PLLRDYCn     = 20
	PLLI2SRDYCn  = 21
	CSSCn        = 23
)

const (
	GPIOARST AHB1RSTR = 0x01 << 0  //+
	GPIOBRST AHB1RSTR = 0x01 << 1  //+
	GPIOCRST AHB1RSTR = 0x01 << 2  //+
	GPIODRST AHB1RSTR = 0x01 << 3  //+
	GPIOERST AHB1RSTR = 0x01 << 4  //+
	GPIOHRST AHB1RSTR = 0x01 << 7  //+
	CRCRST   AHB1RSTR = 0x01 << 12 //+
	DMA1RST  AHB1RSTR = 0x01 << 21 //+
	DMA2RST  AHB1RSTR = 0x01 << 22 //+
)

const (
	GPIOARSTn = 0
	GPIOBRSTn = 1
	GPIOCRSTn = 2
	GPIODRSTn = 3
	GPIOERSTn = 4
	GPIOHRSTn = 7
	CRCRSTn   = 12
	DMA1RSTn  = 21
	DMA2RSTn  = 22
)

const (
	OTGFSRST AHB2RSTR = 0x01 << 7 //+
)

const (
	OTGFSRSTn = 7
)

const (
	TIM2RST   APB1RSTR = 0x01 << 0  //+
	TIM3RST   APB1RSTR = 0x01 << 1  //+
	TIM4RST   APB1RSTR = 0x01 << 2  //+
	TIM5RST   APB1RSTR = 0x01 << 3  //+
	WWDGRST   APB1RSTR = 0x01 << 11 //+
	SPI2RST   APB1RSTR = 0x01 << 14 //+
	SPI3RST   APB1RSTR = 0x01 << 15 //+
	USART2RST APB1RSTR = 0x01 << 17 //+
	I2C1RST   APB1RSTR = 0x01 << 21 //+
	I2C2RST   APB1RSTR = 0x01 << 22 //+
	I2C3RST   APB1RSTR = 0x01 << 23 //+
	PWRRST    APB1RSTR = 0x01 << 28 //+
)

const (
	TIM2RSTn   = 0
	TIM3RSTn   = 1
	TIM4RSTn   = 2
	TIM5RSTn   = 3
	WWDGRSTn   = 11
	SPI2RSTn   = 14
	SPI3RSTn   = 15
	USART2RSTn = 17
	I2C1RSTn   = 21
	I2C2RSTn   = 22
	I2C3RSTn   = 23
	PWRRSTn    = 28
)

const (
	TIM1RST   APB2RSTR = 0x01 << 0  //+
	USART1RST APB2RSTR = 0x01 << 4  //+
	USART6RST APB2RSTR = 0x01 << 5  //+
	ADCRST    APB2RSTR = 0x01 << 8  //+
	SDIORST   APB2RSTR = 0x01 << 11 //+
	SPI1RST   APB2RSTR = 0x01 << 12 //+
	SPI4RST   APB2RSTR = 0x01 << 13 //+
	SYSCFGRST APB2RSTR = 0x01 << 14 //+
	TIM9RST   APB2RSTR = 0x01 << 16 //+
	TIM10RST  APB2RSTR = 0x01 << 17 //+
	TIM11RST  APB2RSTR = 0x01 << 18 //+
	SPI5RST   APB2RSTR = 0x01 << 20 //+
)

const (
	TIM1RSTn   = 0
	USART1RSTn = 4
	USART6RSTn = 5
	ADCRSTn    = 8
	SDIORSTn   = 11
	SPI1RSTn   = 12
	SPI4RSTn   = 13
	SYSCFGRSTn = 14
	TIM9RSTn   = 16
	TIM10RSTn  = 17
	TIM11RSTn  = 18
	SPI5RSTn   = 20
)

const (
	GPIOAEN AHB1ENR = 0x01 << 0  //+
	GPIOBEN AHB1ENR = 0x01 << 1  //+
	GPIOCEN AHB1ENR = 0x01 << 2  //+
	GPIODEN AHB1ENR = 0x01 << 3  //+
	GPIOEEN AHB1ENR = 0x01 << 4  //+
	GPIOHEN AHB1ENR = 0x01 << 7  //+
	CRCEN   AHB1ENR = 0x01 << 12 //+
	DMA1EN  AHB1ENR = 0x01 << 21 //+
	DMA2EN  AHB1ENR = 0x01 << 22 //+
)

const (
	GPIOAENn = 0
	GPIOBENn = 1
	GPIOCENn = 2
	GPIODENn = 3
	GPIOEENn = 4
	GPIOHENn = 7
	CRCENn   = 12
	DMA1ENn  = 21
	DMA2ENn  = 22
)

const (
	OTGFSEN AHB2ENR = 0x01 << 7 //+
)

const (
	OTGFSENn = 7
)

const (
	TIM2EN   APB1ENR = 0x01 << 0  //+
	TIM3EN   APB1ENR = 0x01 << 1  //+
	TIM4EN   APB1ENR = 0x01 << 2  //+
	TIM5EN   APB1ENR = 0x01 << 3  //+
	WWDGEN   APB1ENR = 0x01 << 11 //+
	SPI2EN   APB1ENR = 0x01 << 14 //+
	SPI3EN   APB1ENR = 0x01 << 15 //+
	USART2EN APB1ENR = 0x01 << 17 //+
	I2C1EN   APB1ENR = 0x01 << 21 //+
	I2C2EN   APB1ENR = 0x01 << 22 //+
	I2C3EN   APB1ENR = 0x01 << 23 //+
	PWREN    APB1ENR = 0x01 << 28 //+
)

const (
	TIM2ENn   = 0
	TIM3ENn   = 1
	TIM4ENn   = 2
	TIM5ENn   = 3
	WWDGENn   = 11
	SPI2ENn   = 14
	SPI3ENn   = 15
	USART2ENn = 17
	I2C1ENn   = 21
	I2C2ENn   = 22
	I2C3ENn   = 23
	PWRENn    = 28
)

const (
	TIM1EN   APB2ENR = 0x01 << 0  //+
	USART1EN APB2ENR = 0x01 << 4  //+
	USART6EN APB2ENR = 0x01 << 5  //+
	ADC1EN   APB2ENR = 0x01 << 8  //+
	SDIOEN   APB2ENR = 0x01 << 11 //+
	SPI1EN   APB2ENR = 0x01 << 12 //+
	SPI4EN   APB2ENR = 0x01 << 13 //+
	SYSCFGEN APB2ENR = 0x01 << 14 //+
	TIM9EN   APB2ENR = 0x01 << 16 //+
	TIM10EN  APB2ENR = 0x01 << 17 //+
	TIM11EN  APB2ENR = 0x01 << 18 //+
	SPI5EN   APB2ENR = 0x01 << 20 //+
)

const (
	TIM1ENn   = 0
	USART1ENn = 4
	USART6ENn = 5
	ADC1ENn   = 8
	SDIOENn   = 11
	SPI1ENn   = 12
	SPI4ENn   = 13
	SYSCFGENn = 14
	TIM9ENn   = 16
	TIM10ENn  = 17
	TIM11ENn  = 18
	SPI5ENn   = 20
)

const (
	GPIOALPEN AHB1LPENR = 0x01 << 0  //+
	GPIOBLPEN AHB1LPENR = 0x01 << 1  //+
	GPIOCLPEN AHB1LPENR = 0x01 << 2  //+
	GPIODLPEN AHB1LPENR = 0x01 << 3  //+
	GPIOELPEN AHB1LPENR = 0x01 << 4  //+
	GPIOHLPEN AHB1LPENR = 0x01 << 7  //+
	CRCLPEN   AHB1LPENR = 0x01 << 12 //+
	FLITFLPEN AHB1LPENR = 0x01 << 15 //+
	SRAM1LPEN AHB1LPENR = 0x01 << 16 //+
	DMA1LPEN  AHB1LPENR = 0x01 << 21 //+
	DMA2LPEN  AHB1LPENR = 0x01 << 22 //+
)

const (
	GPIOALPENn = 0
	GPIOBLPENn = 1
	GPIOCLPENn = 2
	GPIODLPENn = 3
	GPIOELPENn = 4
	GPIOHLPENn = 7
	CRCLPENn   = 12
	FLITFLPENn = 15
	SRAM1LPENn = 16
	DMA1LPENn  = 21
	DMA2LPENn  = 22
)

const (
	OTGFSLPEN AHB2LPENR = 0x01 << 7 //+
)

const (
	OTGFSLPENn = 7
)

const (
	TIM2LPEN   APB1LPENR = 0x01 << 0  //+
	TIM3LPEN   APB1LPENR = 0x01 << 1  //+
	TIM4LPEN   APB1LPENR = 0x01 << 2  //+
	TIM5LPEN   APB1LPENR = 0x01 << 3  //+
	WWDGLPEN   APB1LPENR = 0x01 << 11 //+
	SPI2LPEN   APB1LPENR = 0x01 << 14 //+
	SPI3LPEN   APB1LPENR = 0x01 << 15 //+
	USART2LPEN APB1LPENR = 0x01 << 17 //+
	I2C1LPEN   APB1LPENR = 0x01 << 21 //+
	I2C2LPEN   APB1LPENR = 0x01 << 22 //+
	I2C3LPEN   APB1LPENR = 0x01 << 23 //+
	PWRLPEN    APB1LPENR = 0x01 << 28 //+
)

const (
	TIM2LPENn   = 0
	TIM3LPENn   = 1
	TIM4LPENn   = 2
	TIM5LPENn   = 3
	WWDGLPENn   = 11
	SPI2LPENn   = 14
	SPI3LPENn   = 15
	USART2LPENn = 17
	I2C1LPENn   = 21
	I2C2LPENn   = 22
	I2C3LPENn   = 23
	PWRLPENn    = 28
)

const (
	TIM1LPEN   APB2LPENR = 0x01 << 0  //+
	USART1LPEN APB2LPENR = 0x01 << 4  //+
	USART6LPEN APB2LPENR = 0x01 << 5  //+
	ADC1LPEN   APB2LPENR = 0x01 << 8  //+
	SDIOLPEN   APB2LPENR = 0x01 << 11 //+
	SPI1LPEN   APB2LPENR = 0x01 << 12 //+
	SPI4LPEN   APB2LPENR = 0x01 << 13 //+
	SYSCFGLPEN APB2LPENR = 0x01 << 14 //+
	TIM9LPEN   APB2LPENR = 0x01 << 16 //+
	TIM10LPEN  APB2LPENR = 0x01 << 17 //+
	TIM11LPEN  APB2LPENR = 0x01 << 18 //+
	SPI5LPEN   APB2LPENR = 0x01 << 20 //+
)

const (
	TIM1LPENn   = 0
	USART1LPENn = 4
	USART6LPENn = 5
	ADC1LPENn   = 8
	SDIOLPENn   = 11
	SPI1LPENn   = 12
	SPI4LPENn   = 13
	SYSCFGLPENn = 14
	TIM9LPENn   = 16
	TIM10LPENn  = 17
	TIM11LPENn  = 18
	SPI5LPENn   = 20
)

const (
	LSEON  BDCR = 0x01 << 0  //+
	LSERDY BDCR = 0x01 << 1  //+
	LSEBYP BDCR = 0x01 << 2  //+
	LSEMOD BDCR = 0x01 << 3  //+
	RTCSEL BDCR = 0x03 << 8  //+
	RTCEN  BDCR = 0x01 << 15 //+
	BDRST  BDCR = 0x01 << 16 //+
)

const (
	LSEONn  = 0
	LSERDYn = 1
	LSEBYPn = 2
	LSEMODn = 3
	RTCSELn = 8
	RTCENn  = 15
	BDRSTn  = 16
)

const (
	LSION    CSR = 0x01 << 0  //+
	LSIRDY   CSR = 0x01 << 1  //+
	RMVF     CSR = 0x01 << 24 //+
	BORRSTF  CSR = 0x01 << 25 //+
	PINRSTF  CSR = 0x01 << 26 //+
	PORRSTF  CSR = 0x01 << 27 //+
	SFTRSTF  CSR = 0x01 << 28 //+
	IWDGRSTF CSR = 0x01 << 29 //+
	WWDGRSTF CSR = 0x01 << 30 //+
	LPWRRSTF CSR = 0x01 << 31 //+
)

const (
	LSIONn    = 0
	LSIRDYn   = 1
	RMVFn     = 24
	BORRSTFn  = 25
	PINRSTFn  = 26
	PORRSTFn  = 27
	SFTRSTFn  = 28
	IWDGRSTFn = 29
	WWDGRSTFn = 30
	LPWRRSTFn = 31
)

const (
	MODPER    SSCGR = 0x1FFF << 0  //+
	INCSTEP   SSCGR = 0x7FFF << 13 //+
	SPREADSEL SSCGR = 0x01 << 30   //+
	SSCGEN    SSCGR = 0x01 << 31   //+
)

const (
	MODPERn    = 0
	INCSTEPn   = 13
	SPREADSELn = 30
	SSCGENn    = 31
)

const (
	PLLI2SM PLLI2SCFGR = 0x3F << 0  //+
	PLLI2SN PLLI2SCFGR = 0x1FF << 6 //+
	PLLI2SR PLLI2SCFGR = 0x07 << 28 //+
)

const (
	PLLI2SMn = 0
	PLLI2SNn = 6
	PLLI2SRn = 28
)

const (
	TIMPRE DCKCFGR = 0x01 << 24 //+
)

const (
	TIMPREn = 24
)
